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Zoom link : https://univ-grenoble-alpes-fr.zoom.us/j/91808901596?pwd=UWZ2cml2N1VBOEZBenk0d3RJek9rdz09
Salle Rémy Lemaire : jauge limitée à 20 personnes
Abstract:
Over the last fifty years, the CMOS (Complementary-Metal-Oxide-Semiconductor) electronics industry has been continuously scaling down transistors in size, to increase performance and reduce power consumption. Nowadays, the smallest transistors in industry achieve 5nm features. As a result, those silicon structures tend to exhibit undesirable quantum effects for a classical transistor which appear to be new research opportunities for quantum information processing.
In particular, it is nowadays possible to trap single electron spins in silicon quantum dots and perform high fidelity quantum gates (i). These demonstrations combined with the intrinsic properties of the silicon lattice (low spin orbit and hyperfine interaction) make CMOS device an excellent candidate for scalable quantum architectures.
This presentation, will focus on the probing of electronic spins trapped in a CMOS device. In the first part I will present the basic characterization of a single electron spin and valley physics detected by standard charge sensing (ii). In the second part, I will show how we can operate a small array of quantum dot (iii) and how we can measure spin states inside. Finally, I’ll present the measurement of higher spin states by probing the quantum capacitance of the system (iv) and how we intend to scale up this measurement technique.
(i) Veldhorst, M. et al. Nat. Nanotechnol. 9, 981 (2014).
(ii) Spence, C. et al. In preparation (2021).
(iii) Chanrion, E. et al. Phys. Rev. Appl. (2020).
(iv) Lundberg, T. et al. Phys. Rev. X (2020).
